The DARPA Information Exploitation Office (IXO) is requesting information from vendors capable of developing and fabricating Application Specific Integrated Circuit (ASIC) chips to support the development of an RF tracking device. Based on the current design of this device, two separate ASIC chips are required: one digital and one analog. While it is preferred that a vendor be capable of developing, designing, and fabricating both chips, DARPA reserves the right to consider vendors with the ability to only develop, design, and fabricate one type of ASIC. A Government laboratory has performed the initial development and design work on these components and has used MOSIS and the IBM trusted foundry processes for limited fabrication of both digital and analog ASICs to demonstrate the basic functionality of these components. The digital ASIC was fabricated using the 8RF process and 7HP was used for the analog ASIC. However, DARPA is now interested in completing the development and design through a commercial source to support the ?commoditization? of these devices and to reduce the overall risks of large-scale manufacturing. The analog ASIC contains the following basic components, in addition to related peripherals: A low noise receiver of GPS signals; Analog-to-digital converter (ADC); Digital-to-analog converter (DAC); Two stage class E transmit amplifier that produces about 17dBm of output power in the S-band frequency range; Phase locked loops for both receiver and transmitter. The digital ASIC contains the following basic components, in addition to related peripherals: ;Specialized GPS signal processor implemented in VHDL code; ARM7TDMI CPU; Memory - 128kB OS RAM, 4kB ROM, 256kB scratch RAM; Memory controller; Binary waveform generator; Power conditioning circuits for both digital and analog ASIC. Design information for both the digital and analog ASICs will be provided by the Government to vendors selected as the result of this RFI so that they may prepare proposals for the completion of the design and fabrication of these components. DARPA plans to host a Workshop to familiarize selected vendors with the goals of this development effort at a date to be announced. Attendance will be by invitation only based upon a technical review of white paper submissions, clearance capabilities and ITAR restrictions. DARPA invites responses from all qualified vendors interested in participating in the Workshop for these components. However, note that due to programmatic requirements, prospective vendors MUST have the following capabilities: 1. All personnel involved in the chip design and layout of these components to have minimum DoD final SECRET clearances. 2. Due to ITAR restrictions, all ASIC chip design and fabrication facilities are to be located within the continental United States. Interested and qualified vendors should submit brief white papers to
[email protected] no later than 1400 EST, Tuesday, 11 December 2007. These white papers should not exceed 6 pages, including figures and/or tables, and should summarize the capabilities of the vendor to perform the necessary development, design and fabrication tasks for the digital and analog ASICs. Pages in excess of the 6-page maximum will not be read by the reviewers. This summary should specifically address the selection criteria listed below. If respondents plan to use another vendor for fabrication, this should be indicated and the credentials and experience of that vendor also to be provided in the white paper. These white papers will be reviewed and selection for further consideration will be based on the following criteria: 1. Demonstrated capabilities and experience in the fabrication of similar ASIC components within the past 3 years 2. Applicability and version of available design tools and how these tools are used to design, predict and verify the performance of the ASICs as they pertain to the above listed features 3. Fabrication facilities and experience with similar ASIC fabrication and how the respondent will process prototype fabrication runs of approximately 100 ASIC chips of each type, as well as large scale production runs of >1,000 ASIC chips of each type. 4. Experience of likely lead personnel should the vendor be selected for further consideration INSTRUCTIONS TO RESPONDERS DARPA appreciates responses from all capable and qualified sources. White papers should adhere to the following formatting and outline instructions: 1. Format specifications include 12-point font, single spaced, single-sided, 8.5 by 11 inches paper, with 1-inch margins. All submissions must be submitted via email to
[email protected] and be in one of the following formats: Microsoft Word, or Adobe PDF. Embedded figures or tables in other formats are permitted, provided the page limit is not exceeded. 2. Cover Page (1 page) a. Title b. Organization c. Responder?s technical and administrative points of contact (names, addresses, phones and fax numbers, and email addresses) d. A sentence indicating if the respondent is capable of developing and fabricating both digital and analog ASIC chips, or only one type of ASIC chip (specify which). 3. Technical Response (5 pages maximum) a. Executive summary b. Discussion of capabilities, to include: i. Specific examples of similar work performed within the past 3 years ii. Descriptions of applicable?and available?design tools and how they will be utilized iii. Description of fabrication processes and facilities capable of producing both prototype and full scale production quantities of ASIC chips iv. Credentials and experience of lead personnel likely to be selected to perform the design and fabrication tasks should the vendor be selected for further participation. DISCLAIMERS AND IMPORTANT NOTES This is an RFI issued solely for information and program planning purposes; this RFI does not constitute a formal solicitation for proposals or proposal abstracts. In accordance with FAR 15.201(e), responses to this notice are not offers and cannot be accepted by the Government to form a binding contract. Submission of a white paper, and/or attendance at any subsequent Workshop, is strictly voluntary and is not required to propose to subsequent Broad Agency Announcements (if any) or research solicitations (if any) on this topic.. DARPA will not provide reimbursement for costs incurred in responding to this RFI or participating in any subsequent Workshop. NO PROPRIETARY OR CLASSIFIED INFORMATION SHOULD BE INCLUDED IN THE RFI RESPONSE. Respondents are advised that DARPA is under no obligation to acknowledge receipt of the information received, or provide feedback to respondents with respect to any information submitted under this RFI. Responses to this RFI do not bind DARPA to any further actions, to include hosting a Workshop or requesting follow-on proposals from vendors responding to this RFI. Submissions may be reviewed by: the Government (DARPA and partners); Federally Funded R&D Centers (such as MIT Lincoln Laboratory); and Systems Engineering and Technical Assistance (SETA) contractors (such as Schafer Corporation, SET Associates, CACI International, and System Analysis, Inc.). POINT OF CONTACT Stephen C. Davis, Contracting Officer, Email
[email protected]. ANY INQUIRIES ON THIS RFI MUST BE SUBMITTED TO
[email protected]. NO TELEPHONE INQUIRIES WILL BE ACCEPTED.