Process Development for and Fabrication of APSM Set and Overlay Metrology Wafers

GENERAL INFORMATION This is combined sources sought notice and notice of intent to sole source. The purpose of this so notice is to conduct market research and identify potential sources of commercial products/services that satisfy the Government’s anticipated needs. If no alternate sources are identified, as a result of this notice, the Government intends to issue a sole source award to AMAG CONSULTING, LLC, 221 FEATHERWOOD COURT, SCHENECTADY, NY 12303-5704 (UEI: EJTSRE9N1TM6), under the authority of FAR 13.106-1(b)(1)(i). NIST conducted market research from December 2025 through March 2026 by conducting internet searches; utilizing GSA and SAM.gov; reviewing professional journals and published literature; and speaking with colleagues, other professionals, and vendors to determine what sources could meet NIST’s minimum requirements. The results of that market research revealed that only AMAG CONSULTING, LLC, appears to be capable of meeting NIST’s requirements as they are the only vendor that creates attenuated phase shift masks. If other capable vendors are identified as a result of this notice, that information will be reviewed and considered so that the NIST may appropriately solicit for its requirement. The North American Industry Classification System (NAICS) code for this acquisition is 334413, Semiconductor and Related Device Manufacturing, with a Small Business Size Standard of 1,250 employees. This notice does not constitute a Request for Proposal (RFP), Request for Quotation (RFQ), Invitation for Bids (IFB), or any commitment by the Government to issue a solicitation or award a contract. The National Institute of Standards and Technology (NIST) will not pay for any information submitted in response to this notice. Submission of information is voluntary and will not result in any obligation on the part of the Government. NO SOLICITATION DOCUMENTS EXIST AT THIS TIME Requests for solicitation documents will not receive a response. Respondents shall clearly mark any proprietary or restricted information. In the absence of such markings, NIST will assume unlimited rights to all technical data submitted. BACKGROUND The National Institute of Standards and Technology (NIST) Physical Measurement Laboratory (PML), Microsystems and Nanotechnology Division (MND), CHIPS R&D Program (https://www.nist.gov/chips/metrology-community), as part of the CHIPS Act activities (Grand Challenge 5: Modeling and Simulating Semiconductor Manufacturing Processes), is working on developing imaging and measurement solutions for integrated circuit (IC) overlay metrology using a scanning electron microscope (SEM). IC production requires measuring the 3D size, shape, and placement of structures with atomic-level accuracy and consistency. The project, titled “SEM Overlay Metrology Based on Physics Model and Artificial Intelligence,” aims to establish a solid scientific foundation and develop comprehensive solutions for SEM-based overlay and dimensional metrology that improve upon the currently used arbitrary methods. This will enable the design of overlay patterns, data collection, and image analysis to be fully optimized through artificial intelligence, physics-based simulation, and modeling, addressing IC production needs now and in the future. For this work, using state-of-the-art samples with patterns relevant to current IC technologies is essential. The NIST MND requires specialized overlay metrology wafers made with attenuated phase shift masks (APSM). This involves designing and fabricating a set of photomasks tailored for manufacturing wafers with both traditional and advanced IC overlay structures, compatible with SEM-based and other overlay measurement techniques. To create overlay metrology structures, two photomasks are needed one for the base, level 1 for the embedded structures, and another for the top structure, level 2. APS masks are photomasks that use the interference created by phase differences to improve image and pattern resolution in photolithography, making them a state-of-the-art technology. The structures of these overlay metrology wafers will be used to demonstrate that the SEM overlay metrology method, based on a physics model and artificial intelligence developed in this CHIPS Act project, is indeed superior to other techniques. DESCRIPTION OF REQUIREMENT NIST is seeking information from contractors capable of providing at least four overlay metrology wafers made with attenuated phase shift masks (APSM) and the corresponding APSM mask set that meet all listed technical minimum specifications below. Description: Process development for and fabrication of APSM set Technical Specifications One set of a minimum of two, attenuated phase shift masks suitable for the fabrication of overlay metrology wafers with Overlay patterns with box-in-box (BiB), image-based overlay (IBO), advanced imaging metrology (AIM) grating patterns, and Hitachi-type SEM-based overlay (SBO) and pattern designs supplied in a GDSII file by NIST MND; Sets of varying size BiB, IBO, AIM and SBO overlay metrology patterns must be included in the less than 150 mm to smaller than 50 mm range. Overlay patterns with intentional, small, close to 1, 2, 5, and 10 nm variations of known overlay offsets (shifts) must be provided. The masks must be covered with a protective layer to safeguard their integrity. A GDSII-based map with pattern locations and properties (size, type, offset, etc.) must be provided at the time of delivery, including identification of these properties. Documentation about the APSM properties, measurements, and images created during the fabrication process that show suitability. Documentation about the APSM properties, material, and the patterning process shall be provided at the time of delivery. Description: Process development for and fabrication of overlay metrology wafers Technical Specifications A minimum of four 300 mm Si wafers patterned with Box-in-box (BiB), image-based overlay (IBO), advanced imaging metrology (AIM) grating patterns, and Hitachi-type SEM-based overlay (SBO) and pattern designs supplied in a GDSII file by NIST MND; Sets of varying size BiB, IBO, AIM and SBO overlay metrology patterns must be included in the less than 150 mm to smaller than 50 mm range. Overlay patterns with intentional, small, close to 1, 2, 5, and 10 nm variations of known overlay offsets (shifts) must be provided. The wafers must be delivered in a clean-room-compatible enclosure to safeguard the integrity of the Cu patterns. A GDSII-based map with pattern locations and properties (size, type, offset, etc.) must be provided at the time of delivery, including identification of these properties. Documentation of the wafer properties, measurements, and images created during the fabrication process that demonstrate suitability shall be provided at the completion of the wafer fabrication process. Documentation about the wafer materials, dopant type, and concentration, and the patterning process shall be provided at the time of delivery. RESPONSE INSTRUCTIONS Interested parties shall submit a written capability statement addressing the following: Company name, address, Unique Entity Identifier (UEI) number, CAGE code, and point-of-contact information Business size and socio-economic status (if applicable) for the NAICS code provided Description of company capabilities relevant to the products/services described above Description of prior experience providing/performing similar products/services described above Identification of applicable contract vehicles (e.g., GSA FSS, GWACs), including contract numbers Any other information the Government should consider for market research purposes State whether the proposed product is manufactured in the United States and, if not, state the name of the country where the product is manufactured. SUBMISSION REQUIREMENTS All responses to this notice must be submitted via email to [email protected] no later than 12:00 PM EST on May 14, 2026. Format: Microsoft Word or PDF Page Limit: 12 pages maximum Font: Times New Roman, 11-point Paper Size: 8.5 x 11 inches Margins: Minimum 1 inch on all sides Any questions regarding this notice must be submitted in writing via email to [email protected], no later than 11:00 AM EST on May 5, 2026.